It is known that the operation speed of mask ROM depends on the gate width of a cell transistor. Since the gate width is increased as the number of bit lines connected to one cell transistor is increased, it is possible to improve the operation speed. Therefore, for example, mask ROM that connects three bit lines to one cell transistor and stores four-valued data based on whether or not each bit line is connected to the cell transistor has been proposed.
However, if a plurality of bit lines is connected to one cell transistor, the potential of adjacent bit lines can be altered due to the influence of the coupling noise between the plurality of bit lines. In particular, with current mask ROM devices, which are driven at a low voltage, there is a possibility that the value exceeds the operation threshold value of a next-stage circuit as a result of potential fluctuations of the adjacent bit line, which may cause an unintended activation.